Current-saving operation is striven for in digital circuit arrangements operated in clocked fashion. In this case, the processing speed associated with the system clock is intended to be as high as possible without exceeding a predetermined maximum average current consumption of the circuit arrangement. The maximum permissible average current consumption results for example due to design dictates or on account of a standardization. A circuit arrangement with a microprocessor used in a smart card is just one example of a circuit arrangement having a predetermined maximum permissible average current consumption.
A circuit arrangement comprises a multiplicity of circuit sections which interact during operation. Circuit sections may be formed for example as a memory, as an arithmetic unit or as logic elements. Since it is usually the case that not all of the circuit sections are operated simultaneously, some circuit sections are switched on and off or have a variable current consumption, the average current consumption of the circuit arrangement varies during operation.
In order to ensure that a predetermined current consumption, also referred to as current limit, is not exceeded, the constant system clock frequency with which the circuit arrangement is clocked can be reduced to an extent such that under the worst possible operating conditions, which depend inter alia on the temperature and the processing, the current limit is not exceeded. Through operation with the current limiting frequency determined in this way, the current limit is on no account exceeded. A disadvantage is that the current consumption approximately reaches the current limit only under the worst possible conditions. The average current consumption is usually far below the current limit.
A further approach for ensuring the current consumption below the current limit and for operating the system with higher system clocking unless the worst possible conditions occur is adaptive clock masking out.
In each clock cycle, a process step is processed in a circuit section within the time duration predetermined by the pulse width. The supply voltage is provided for processing purposes. The processing is accompanied by the charge reversal of parasitic capacitances. The charge reversal has to be effected within the predetermined pulse duration. Consequently, a shorter pulse duration requires a higher supply voltage.
In the case of clock masking out, individual clock cycles are suppressed so that the effective system clock frequency decreases. Effective system clock frequency is to be understood to mean the average system clock frequency, depending on the pulses of the clocking signal which occur on average. Since, in the case of clock masking out, time segments with pulses at a clock frequency are followed by time segments in which no pulses are output, the effective system clock frequency is lower than the clock frequency. The length of the individual pulses is not changed by the clock masking out.
A disadvantage of the method described above is that the constantly high supply voltage is accompanied by an inefficiently high current consumption, since the latter is proportional to the supply voltage.